1. Field of the Invention
The present invention relates to an image processing apparatus and an image reception/reproduction apparatus using the same and, more particularly, to an image reception/reproduction apparatus for reproducing an image signal from image information received from a transfer medium or reproduction image information from a recording medium.
2. Related Background Art
An arrangement of a conventional image reception/reproduction apparatus used in a television conference system, a television telephone system, or the like is shown in FIG. 6. Image information from a satellite broadcast channel or a communication channel is converted into acompressed digital signal by a reception circuit 10 and is sequentially decoded into an expanded original image signal by a compressed image decoder 12. The image signal decoded by the decoder 12 is written in one of two frame memories 14 and 16 which is not used for monitor display. One of the two frame memories 14 and 16 is used for monitor display (read mode), and the other is used to write a reception image signal. The monitor display memory and the reception 1 image write memory are alternately switched. For example, upon completion of write access of the reception image signal to be written in the frame memory 14 the frame memory 14 then serves as a monitor display frame memory. Meanwhile, the next reception image signal is written in the frame memory 16.
Data read out at a video rate from the display frame memory to be displayed on a monitor 20 is converted into an analog signal by a D/A converter 18. A sync signal is added to the analog signal, and the resultant data is sent to the monitor 20, thereby displaying the reception image. A read address and read timing generation circuit 22 generates a display frame memory read address and a read timing signal.
The two frame memories are alternately used for display and write access due to the following reasons. First, when the decoded reception images are sequentially written in the display memory, contention occurs between the write timings and read timings of the display system, thereby making it difficult to perform proper timing control. Second, when a multiport DRAM is used as a frame memory, the contention between the read and write timings can be prevented. However, a display image is gradually changed from its end with the progress of write access of the reception image, thereby degrading readability of the image.
There is also available a method of preventing a horizontal line from being displayed on the screen by completing switching of the two frame memories within a vertical blanking period.
In the above conventional methods, in order to perform partial transmission for updating part of the image currently displayed on the screen, data corresponding to the currently displayed image must be read out from the frame memory. Only the data subjected to partial transmission is updated, and the updated data must be written in the write frame memory. Even if a partial transmission area is very small, transmission of the data of the entire display area must be transferred, resulting in a long transfer period and a waste of time. For example, in a high definition television, assume that R, G, and B components are simultaneously transmitted. Even if DMA (Direct Memory Access) hardware is added, transmission of the entire frame by the existing circuit elements requires about 0.8 sec. More specifically, the total transfer time is 794 ms (=1920.times.1035.times.200 ns.times.2) when the number of horizontal pixels is 1,920, the number of vertical pixels is 1,035, a DRAM parallel port cycle time is 200 ns, and the number of read and write cycles is 2.
When a processor such as a DSP (Digital Signal Processor) in a compressed image decoder performs transmission of the entire image or frame without using DMA hardware, a total transmission time is undesirably prolonged several times, thus resulting in impractical applications.